In semi-conductor memory components a distinction is made between so-called function memory components (e.g. PLAs, PALs, etc.), and so-called table memory components, e.g. ROM-components (ROM=Read Only Memory and/or non-volatile memory), and RAM-components (RAM=Random Access Memory and/or write/read memory).
A RAM component is a memory device, in which data is stored after an address has been specified, which data can later be read out again under that address.
The corresponding address can be entered into the RAM component via so-called address connections or address input pins. Several, e.g. 16 so-called data connections and/or data-input/output pins (I/Os) are provided for inputting or outputting data. By applying a corresponding signal (e.g. a read/write signal) to a write/read selection connection and/or pin, it can be (instantly) determined whether data is to be stored or read out.
Because as many memory cells as possible must be accommodated in a RAM component, it is important for the former to be created as simply as possible. In so-called SRAMs (SRAM=Static Random Access Memory) the individual memory cells consist of only a few, e.g. six transistors, and in so-called DRAMs (DRAM=Dynamic Random Access Memory) usually consist of a single appropriately controlled capacitor, the capacitance of which can be used to store one bit as a charge. This charge however persists only for a short time; for this reason it needs to “refreshed” regularly, e.g. ca. every 64 ms.
For technological reasons in memory, in particular, DRAM components the individual memory cells are arranged in a multitude of adjacent rows and columns in a rectangular matrix and/or a rectangular array.
In order to achieve a correspondingly high total storage capacity and/or to achieve the highest data reading and/or writing speed,—instead of a single array—several, for instance four—essentially rectangular—(sub-) arrays (so-called “memory banks”) can be arranged in a single RAM component and/or chip (“multi-bank chip”).
In order to perform a writing or reading operation, a specific, unchanging sequence of commands must be issued:
First for instance a corresponding word line specifically allocated to a particular sub-array (“memory bank”) (and defined by the “row address”) is activated by means of a word line activation command (activate command (ACT)).
This allows the corresponding data—exactly specified by the corresponding column address—to be correspondingly output (or read in)—with the help of a corresponding read/write (RD=read, or WT=write) command.
Next the corresponding word line is deactivated again—with the help of a word line deactivation command (e.g. a pre-charge command (PRE command)), and the corresponding sub-array (“memory bank”) prepared for the next word line activation command (ACT=activate command).
In order to guarantee a fault-free operation of the DRAM component, specific chronological conditions must be maintained.
For instance, a particular delay tRCD (the so-called RAS-CAS delay) must occur between the word line activation command (ACT command) and a corresponding read (or write) command (RD (or WT) command). The RAS-CAS delay for instance is a result of the time needed by the sense amplifier to amplify the data delivered by the memory cells addressed by the word line.
Correspondingly a time interval tRP (the so-called “row pre-charge time” delay) must also be maintained between the read (or write) command (RD (or WT) command) and a subsequent word line deactivation command (PRE-command).
Due to the provision of several mutually independent sub-arrays (“memory banks”)—as described above—in a single DRAM component—for which mutually independent corresponding word line activation and deactivation commands are in each case generated by a corresponding memory component control device (“memory controller”)—the delay times—occurring in total for the component during the writing and/or reading of data (for instance because parallel and/or chronologically overlapping corresponding write or read accesses can be performed at several separate sub-arrays (“memory banks”))—can be reduced and the capability of the DRAM component correspondingly increased.
In order to increase the capability of a corresponding DRAM component even more, the relevant word line can at first be left in an activated condition (i.e. the corresponding word line deactivation command (PRE command) can initially be suppressed by the corresponding memory component control device (“memory controller”)—after having output a corresponding word line activation command (ACT command), and a corresponding read (or write) command (RD (or WT) command)).
If—which is statistically relatively common—a memory cell or cells is/are next accessed in the corresponding sub-array (“memory bank”) allocated to the same word line and/or row as that/those memory cell(s) that was/were accessed immediately before, the outputting of a further word line activation command (ACT-command) can be dispensed with.
Instead the memory component control device (“memory controller”) can immediately output a corresponding read (or write) command (RD (or WT) command) to the sub-array (“memory bank”) in question (and thereby it can be achieved that the corresponding data can be immediately read out (or input)—without a corresponding RAS-CAS delay (tRCD) taking place).
Only then—which is statistically much less common—when a memory cell or cells in a corresponding sub-array (“memory bank”) allocated to a different word line or row to that/those memory cell(s) which was/were accessed immediately before, is/are accessed, is the corresponding word line—last used—deactivated by issuing a corresponding word line deactivation command (PRE command), and the—new—word line activated (by issuing a corresponding further word line activation command (ACT command)).